//------------------------------------------------------------------------------
// The confidential and proprietary information contained in this file may
// only be used by a person authorised under and to the extent permitted
// by a subsisting licensing agreement from ARM Limited.
//
//            (C) COPYRIGHT 2008-2012 ARM Limited.
//                ALL RIGHTS RESERVED
//
// This entire notice must be reproduced on all copies of this file
// and copies of this file may only be made by a person if such person is
// permitted to do so under the terms of a subsisting license agreement
// from ARM Limited.
//------------------------------------------------------------------------------
// Version and Release Control Information:
//
// File Revision       : 127275
// File Date           :  2012-03-19 15:37:15 +0000 (Mon, 19 Mar 2012)
// Release Information : PL401-r0p1-00eac0
//------------------------------------------------------------------------------
//
//        *** AUTOMATICALLY GENERATED, ONLY MODIFY MARKED SECTIONS ***
//
//  Purpose:
//  Synchronisation of a signal between two clock domains.
//
//  --=====================================================================--

  


module nic400_ib_chiplink_slv_axi4_tpv_ib_b_fifo_sync_ysyx_rv32
(
   // Inputs
   clk,
   resetn,
   ptr_async,

   // Outputs
   ptr_sync
);

   input           clk;
   input           resetn;
   input  [1:0]    ptr_async;

   output [1:0]    ptr_sync;




   wire   [1:0]    ptr_corrupt;

//------------------------------------------------------------------------------
// Main Code
//------------------------------------------------------------------------------

   // Test component to corrupt pointer going into synchroniser
   nic400_cdc_corrupt_gry_ysyx_rv32 #(2) u_cdc_corrupt_ptr
   (
      .clk       (clk), 
      .resetn    (resetn), 
      .sync      (1'b0),
      .d_async   (ptr_async),
      .q_async   (ptr_corrupt)
   );

   //instance cdc_capt_sync blocks
nic400_cdc_capt_sync_ysyx_rv32 #(1) u_cdc_capt_sync_ptr_0
   (
      .clk       (clk),
      .resetn    (resetn),
      .sync_en   (1'b1),
      .d_async   (ptr_corrupt[0]),
      .q         (ptr_sync[0])
   );
nic400_cdc_capt_sync_ysyx_rv32 #(1) u_cdc_capt_sync_ptr_1
   (
      .clk       (clk),
      .resetn    (resetn),
      .sync_en   (1'b1),
      .d_async   (ptr_corrupt[1]),
      .q         (ptr_sync[1])
   );

endmodule


// --================================= End ===================================--
